Analog Microelectronics, Inc.

10

AME811/AME811A/AME811R

3-1/2 Digit A/D Converter - Low Power

With HOLD And Differential Reference Inputs

Test

When the TEST is pulled to V+ all segments and the

minus sign will be activated. The TEST pin is tied to

the internally generated digital ground through a 500

Ω

resistor in the AME811. It is typically 5V lower than V+.

TEST pin may be used as the negative power supply

for external CMOS logic at the maximum current of 1

mA.

Data Hold

When the Hold pin is connected to V+ the conversion

result will not be updated. The conversion is still free

running during the hold mode.

Integration Status (INTEN)

The INTEN is an output signal of the converter, it is

“high” during the signal integration phase. This signal

can be used as a status indicator or a control to con-

nect the analog signal to the converter for processing.

It is available in 44 pin package.

De-integration Status (DEEN)

The DEEN is an output signal of the converter, it is

“high” during the reference de-integration phase. The

period of the DEEN is proportional to the conversion

result. Users may calculate the conversion result by

counting the number of clock pulse on the OSC3 pin

when DEEN is “high”. The conversion result is equal

to (N /4) - 1/2 where N is the number of the pulse at the

OSC3 pin. It is available in 44 pin package.

n

n

n

n

Auto-Zero Capacitor (Caz)

The Caz capacitor size has some influence on system

noise. A 0.47

µF capacitor is recommended for 200

mV full-scale applications. A 0.047

µF capacitor is rec-

ommended for 2.0V full-scale applications. A mylar

dielectric capacitor is adequate.

Reference Capacitor (Cref)

A 0.1

µF capacitor is acceptable when “INLO” is tied

to analog common. If a large common-mode voltage

exists and the application requires 200 mV full-scale,

increase Cref to 1.0

µF. A mylar dielectric capacitor is

adequate.