PSD813F2 datasheet(82/128 Pages) STMICROELECTRONICS

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Power management

PSD8XXFX

82/128

Doc ID 7833 Rev 7

Figure 32.

Enable Power-down flowchart

17.4

PLD power management

The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in PMMR0. By

setting the bit to '1,' the Turbo mode is off and the PLDs consume the specified standby

current when the inputs are not switching for an extended time of 70ns. The propagation

delay time is increased by 10ns after the Turbo Bit is set to '1' (turned off) when the inputs

change at a composite frequency of less than 15 MHz. When the Turbo Bit is reset to '0'

(turned on), the PLDs run at full power and speed. The Turbo Bit affects the PLD’s DC

power, AC power, and propagation delay.

Blocking MCU control signals with the bits of PMMR2 can further reduce PLD AC power

consumption.

Enable APD

Set PMMR0 Bit 1 = 1

PSD in Power

Down Mode

ALE/AS idle

for 15 CLKIN

clocks?

RESET

Yes

OPTIONAL

Disable desired inputs to PLD

by setting PMMR0 bits 4 and 5

and PMMR2 bits 2 through 6.

AI02892

Table 31.

Power Management mode registers PMMR0(1)

Bit

Name

Description

Bit 0

Not used, and should be set to zero.

Bit 1

APD Enable

0 =

off

Automatic Power-down (APD) is disabled.

1 =

Automatic Power-down (APD) is enabled.

Bit 2

Not used, and should be set to zero.

Bit 3

PLD Turbo

0 =

PLD Turbo mode is on

1 =

off

PLD Turbo mode is off, saving power.

Obsolete

Product(s)

- Obsolete

Product(s)

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