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A43L0616AV データシート(PDF) 29 Page - AMIC Technology |
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A43L0616AV データシート(HTML) 29 Page - AMIC Technology |
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29 / 45 page ![]() A43L0616A (May, 2001, Version 1.0) 28 AMIC Technology, Inc. Page Write Cycle at Different Bank @Burst Length=4 High 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE CS RAS CAS ADDR BA Row Active with (A-Bank) Write (A-Bank) : Don't care RAa CAa A10/AP CBb Write (B-Bank) Row Active (B-Bank) RBb CAc RAa RBb WE DBb1 DBb0 DAa0 DAa1 DAa2 DAa3 DBb2 DBb3 DAc0 DAc1 Write (A-Bank) Precharge (Both Banks) DQM DQ tCDL DBd0 DBd1 *Note 2 CBd tRDL *Note 1 Write (B-Bank) * Note: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and precharge banks must be the same. |
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