Timing diagrams

STP16CPC26

12/26

Doc ID 18469 Rev 4

8

Timing diagrams

The timing diagram shown in

Figure 11 and the truth table in Table 7 explain how to send

data to the device. This can be summarized in the following points:

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LE and OE are level sensitive and not synchronized with the CLK signal

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When LE is at low level, the latch circuit holds previous data

●

If LE is high level, data present in the shift register are latched

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When OE is at low level, the status of the outputs OUT0 to OUT15 depends on the data

in the latch circuits

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With OE at high level, all outputs are switched off independently on the data stored in

the latch circuits

●

Every rising edge of the CLK signal, a new data on SDI pin is sampled. This data is

loaded into the shift register, whereas a bit is shifted out from SDO.

Figure 11.

Timing diagram