AD7631BSTZ datasheet(6/32 Pages) AD

部品番号	AD7631BSTZ

部品情報	18-Bit, 250 kSPS, Differential Programmable Input PulSAR짰 ADC

PDF	32 Pages

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メーカー	AD [Analog Devices]

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6 / 32 page

AD7631

Rev. A | Page 6 of 32

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1]

DIVSCLK[0]

Symbol

Unit

SYNC to SDCLK First Edge Delay Minimum

t18

Internal SDCLK Period Minimum

t19

120

240

Internal SDCLK Period Maximum

t19

180

360

Internal SDCLK High Minimum

t20

120

Internal SDCLK Low Minimum

t21

115

SDOUT Valid Setup Time Minimum

t22

SDOUT Valid Hold Time Minimum

t23

SDCLK Last Edge to SYNC Delay Minimum

t24

BUSY High Width Maximum

t28

2.55

3.40

5.00

8.20

μs

NOTES

1. IN SERIAL INTERFACE MODES, THE SYNC, SDCLK,

AND SDOUT ARE DEFINED WITH A MAXIMUM LOAD

CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

1.6mA

IOL

500µA

IOH

1.4V

TO OUTPUT

60pF

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SDCLK Outputs, CL = 10 pF

0.8V

tDELAY

Figure 3. Voltage Reference Levels for Timing

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