www.austriamicrosystems.com/AS3643

1.5-4

19 - 33

AS3643

Datasheet, Confidential - D e ta i l e d D e s c r i p t i o n

Figure 27. Data Transfer on I

Depending upon the state of the R/W bit, two types of data transfer are possible:

1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the

slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received

byte. Data is transferred with the most significant bit (MSB) first.

2. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave

address). The slave then returns an acknowledge bit, followed by the slave transmitting a number of data

bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the

last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock pulses

and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START

condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not

released. Data is transferred with the most significant bit (MSB) first.

The AS3643 can operate in the following two modes:

1. Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each

byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the begin-

ning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave

address and direction bit (see Figure 28). The slave address byte is the first byte received after the master

generates the START condition. The slave address byte contains the 7-bit AS3643 address, which is 0110000,

followed by the direction bit (R/W), which, for a write, is 0.

byte the device outputs an acknowledge on the SDA line. After the AS3643 acknowledges the slave address +

write bit, the master transmits a register address to the AS3643. This sets the register pointer on the AS3643.

The master may then transmit zero or more bytes of data, with the AS3643 acknowledging each byte received.

The address pointer will increment after each data byte is transferred. The master generates a STOP condition

to terminate the data write.

2. Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode.

However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmit-

ted on SDA by the AS3643 while the serial clock is input on SCL. START and STOP conditions are recognized

as the beginning and end of a serial transfer (Figure 29 and Figure 30). The slave address byte is the first byte

received after the master generates a START condition. The slave address byte contains the 7-bit AS3643

address, which is 0110000, followed by the direction bit (R/W), which, for a read, is 1.

decoding the slave address byte the device outputs an acknowledge on the SDA line. The AS3643 then

begins to transmit data starting with the register address pointed to by the register pointer. If the register

9. The address for writing to the AS3643 is 60h = 01100000b

10.The address for read mode from the AS3643 is 61h = 01100001b

SLAVE

ADDRESS

ACKNOWLEDGEMENT

SIGNAL FROM

RECEIVER

ACKNOWLEDGEMENT

SIGNAL FROM

RECEIVER

REPEATED IF

MORE BYTES ARE

TRANSFERRED

STOP CONDITION

OR REPEATED

START CONDITION

START

CONDITION

SCL

SDA

MSB

R/W

DIRECTION

BIT

ACK

1

2

6

78

9

1

2

3-7

89