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AS5510

Datasheet - Detailed Descr i p ti on

The communication from the AS5510 includes:



Reading the magnetic field strength in 10-bit data



Reading the status bits

Note:

The I²C address of the chip is selected by hardware (pin ADR). Depending on the state of this pin, the I²C address is either

Pin ADR = LOW  I²C address = 1010110b(56h)

Pin ADR = HIGH  I²C address = 1010111b(57h)

7.2.1 I²C Interface Data

Note:

Table 7. I²C Timings

Symbol

Parameter

Conditions

Min

Typ

Max

Units

SCL clock frequency

1

MHz

Bus free time; time between STOP and

START condition

0.5

μs

Hold time; (repeated) START

condition

1

1. After this time the first clock is generated

0.26

μs

LOW period of SCL clock

0.5

μs

HIGH period of SCL clock

0.26

μs

Setup time for a repeated START

condition

0.26

μs

Data hold time

2

bridge the undefined region of the falling edge of SCL.

0.45

μs

Data setup time

3

the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL sig-

50

ns

Rise time of SDA and SCL signals

120

ns

Fall time of SDA and SCL signals

4

4. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used this has to be consid-

ered for bus timing.

120

ns

Setup time for STOP condition

0.26

μs