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SN74LS173N データシート(PDF) 1 Page - Motorola, Inc

部品番号 SN74LS173N
部品情報  4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS
PDF  6 Pages
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メーカー  MOTOROLA [Motorola, Inc]
ホームページ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

SN74LS173N データシート(HTML) 1 Page - Motorola, Inc

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FAST AND LS TTL DATA
4-BIT D-TYPE REGISTER
WITH 3-STATE OUTPUTS
The SN54 / 74LS173A is a high-speed 4-Bit Register featuring 3-state
outputs for use in bus-organized systems. The clock is fully edge-triggered
allowing either a load from the D inputs or a hold (retain register contents)
depending on the state of the Input Enable Lines (IE1, IE2). A HIGH on either
Output Enable line (OE1, OE2) brings the output to a high impedance state
without affecting the actual register contents. A HIGH on the Master Reset
(MR) input resets the Register regardless of the state of the Clock (CP), the
Output Enable (OE1, OE2) or the Input Enable (IE1, IE2) lines.
• Fully Edge-Triggered
• 3-State Outputs
• Gated Input and Output Enables
• Input Clamp Diodes Limit High-Speed Termination Effects
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
CONNECTION DIAGRAM DIP (TOP VIEW)
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
VCC
OE1
MR
D0
D1
D2
IE2
D3
IE1
OE2 Q0
Q1
Q2
Q3
CP
GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
D0 – D3
IE1 – IE2
OE1 – OE2
CP
MR
Q0 – Q3
Data Inputs
Input Enable (Active LOW)
Output Enable (Active LOW) Inputs
Clock Pulse (Active HIGH Going Edge)
Input
Master Reset Input (Active HIGH)
Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 (25) U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 (7.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
SN54/74LS173A
4-BIT D-TYPE REGISTER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXD
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
D0 D1 D2D3
CP
OE
MR
1 2
1
1
2
2
Q1
Q0
Q2Q3
9 10
14 13 12 11
3 4 5 6
15
7
IE


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