CS5331A datasheet(9/30 Pages) CIRRUS

9 / 30 page

LRCK is automatically detected during power-up

and internal dividers are set to generate the ap-

propriate internal clocks.

CS5330A

The CS5330A data output format is shown in

Figure 2. Notice that the MSB is clocked by the

transition of LRCK and the remaining seventeen

data bits are clocked by the falling edge of

SCLK. The data bits are valid during the rising

edge of SCLK.

CS5331A

The CS5331A data output format is shown in

Figure 3. Notice the one SCLK period delay be-

tween the LRCK transitions and the MSB of the

data. The falling edges of SCLK cause the ADC

to output the eighteen data bits. The data bits are

valid during the rising edge of SCLK. LRCK is

also inverted compared to the CS5330A inter-

face. The CS5331A interface is compatible with

2S.

20 21

SCLK

LRCK

Left Audio Data

Right Audio Data

SDATA

Figure 3. Data Output Timing - CS5331A (I

2S compatible)

20 21

SCLK

LRCK

Left Audio Data

Right Audio Data

SDATA

Figure 2. Data Output Timing - CS5330A

CS5330A/CS5331A

DS138F2

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