DS1867 datasheet(6/14 Pages) DALLAS

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DS1867

6 of 14

102199

The Cout output of the DS1867 can be used to drive the DQ input of another DS1867. When connecting

multiple devices, the total number of bits sent is always 17 times the number of DS1867s in the daisy

chain.

An optional feedback resistor can be placed between the Cout terminal of the last device and the DQ input

of the first DS1867, thus allowing the controlling processor to read, as well as, write data or circularly

clock data through the daisy chain. The value of the feedback or isolation resistor should be in the range

from 2 to 10 kohms.

When reading data via the COUT pin and isolation resistor, the DQ line is left floating by the reading

device. When RST is driven high, bit 17 is present on the COUT pin, which is fed back to the input DQ pin

through the isolation resistor. When the CLK input transitions low to high, bit 17 is loaded into the first

position of the I/O shift register and bit 16 becomes present on COUT and DQ of the next device. After 17

bits (or 17 times the number of DS1867s in the daisy chain), the data has shifted completely around and

back to its original position. When RST transitions to the low state to end data transfer, the value (the

same as before the read occurred) is loaded into the wiper-0, wiper-1, and stack select bit I/O register.

CASCADING MULTIPLE DEVICES Figure 5

NONVOLATILE WIPER SETTINGS

The DS1867 maintains the position of the wiper in the absence of power. This feature is provided through

the use of EEPROM type memory cell arrays. During normal operation, the position of the wiper is

determined by the device multiplexers and stored in the shadow memory (EEPROM). The manner in

which an update occurs has been optimized for reliability, durability, and performance. Additionally, the

update operation is totally transparent to the user.

When power is applied to the DS1867, wiper settings will be the last recorded in the EEPROM memory

cells or shadow memory before the last power-down. Changes to the EEPROM memory cells occur

during a predefined power-down sequence. If the DS1867 detects a voltage transition to 4.5 volts or less,

on the power supply input, the part initiates an automatic wiper storage sequence. This storage sequence

will save in EEPROM memory the contents of the I/O shift register before a total power-shutdown;

provided specific power-down timing requirements are met. The minimum total power-down time is

specified at 4 milliseconds. Power-down timing requirements on VCC are shown in Figure 6.

The EEPROM memory cells are specified to accept greater than 25,000 writes before a wear-out

condition. If the EEPROM memory cells do reach a wear-out condition, the DS1867 will still function

properly while power is applied. A minimum time of 4 ms between 4.5V and 3V is required to perform

the proper position storage of the wiper.

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