DS2152L datasheet(2/94 Pages) DALLAS

2 / 94 page

DS2152

2 of 93

TABLE OF CONTENTS

1.0

INTRODUCTION ..................................................................................... 4

Block Diagram...............................................................................................................................

Pin List...........................................................................................................................................

Pin Description ..............................................................................................................................

Register Map..................................................................................................................................

2.0

PARALLEL PORT................................................................................... 17

3.0

CONTROL, ID, AND TEST REGISTERS ................................................ 18

Payload Loopback .........................................................................................................................

Framer Loopback...........................................................................................................................

Pulse Density Enforcer ..................................................................................................................

Local Loopback .............................................................................................................................

Power-up Sequence .......................................................................................................................

Remote Loopback ..........................................................................................................................

4.0

STATUS AND INFORMATION REGISTERS .......................................... 30

5.0

ERROR COUNT REGISTERS ................................................................ 38

Line Code Violation Count Register .............................................................................................

Path Code Violation Count Register..............................................................................................

Multiframes Out of SYNC Count Register ...................................................................................

6.0

DSO MONITORING FUNCTION ............................................................. 41

7.0

SIGNALING OPERATION....................................................................... 44

Processor Based Signaling..........................................................................................................

Hardware Based Signaling..........................................................................................................

8.0

PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK.......... 47

Transmit Side Code Generation.....................................................................................................

Receive Side Code Generation ......................................................................................................

9.0

CLOCK BLOCKING REGISTERS .......................................................... 51

10.0 ELASTIC STORES OPERATION............................................................ 52

11.0 FDL/FS EXTRACTION AND INSERTION................................................ 53

HDLC and BOC Controller for the FDL.......................................................................................

Legacy FDL Support .....................................................................................................................

D4/SLC-96 Operation....................................................................................................................

12.0 PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION 65

13.0 TRANSMIT TRANSPARENCY................................................................ 68

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