VIPER25 datasheet(29/40 Pages) STMICROELECTRONICS

29 / 40 page

VIPER25

Operation description

Doc ID 15585 Rev 4

29/40

The time, from the high load detection, VFB = VFBlin, to the over load turn-off, VFB = VFBolp,

depends from the value of the capacitor CFB and from the internal charge current, IFB. The

OLP delay time can be calculating by the formula:

Equation 8

The current, IFB, is 3 μA as minimum value. The components connected to the FB pin are

also a part of the compensation loop

, so they have to be selected taking into account the

proper delay and loop stability consideration. The Figure 34 on page 30 and Figure 35 on

page 30

show two different feedback networks.

In the Figure 33 on page 27, the capacitor, CFB, connected to FB pin is used as part of the

circuit to compensate the feedback loop but also as element to delay the OLP shut down

owing to the time needed to charge the capacitor (see the Equation 8).

After the start-up time, tSU, during which the feedback voltage is fixed at VFBlin, the output

capacitor could not be at its nominal value and the controller interpreter this situation as an

over load condition. In this case, the OLP delay helps to avoid an incorrect device shut down

during the start-up. See the relevant Section 7.3 on page 16.

Owing to the above considerations, the OLP delay time must be long enough to by-pass the

initial output voltage transient and check the over load condition only when the output

voltage is in steady state. The output transient time depends from the value of the output

capacitor and from the load.

When the value of the CFB capacitor calculated for the loop stability is too low and cannot

ensure enough OLP delay, an alternative compensation network can be used and it is

showed in Figure 35 on page 30.

Using this alternative compensation network, two poles (fPFB, fPFB1) and one zero (fZFB) are

introduced by the capacitors CFB and CFB1 and the resistor RFB1.

The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole

is usually used to compensate the high frequency zero due to the ESR (Equivalent Series

Resistor) of the output capacitance of the fly-back converter.

The mathematical expressions of these poles and zero frequency, considering the scheme

in Figure 35 on page 30 are reported by the equations below:

Equation 9

Equation 10

OLP

delay

–

FBolp

FBlin

–

μA

----------------------------------------

ZFB

⋅

()

)

DYN

(

)

DYN

(

PFB

⋅

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