Functional description

L9822E

10/17

4

Functional description

The L9822E DMOS output is a low operating power device featuring, eight 1

 R

DSON

DMOS drivers with transient protection circuits in output stages.

Each channel is independently controlled by an output latch and a common RESET line

which disables all eight outputs. The driver has low saturation and short circuit protection

and can drive inductive and resistive loads such as solenoids, lamps and relays.

Data is transmitted to the device serially using the Serial Peripheral Interface (SPI) protocol.

The circuit receives 8 bit serial data by means of the serial input (SI) which is stored in an

internal register to control the output drivers. The serial output (SO) provides 8 bit of

diagnostic data representing the voltage level at the driver output. This allows the

microprocessor to diagnose the condition of the output drivers.

The output saturation voltage is monitored by a comparator for an out of saturation condition

and is able to unlatch the particular driver through the fault reset line. This circuit is also

cascadable with another octal driver in order to jam 8 bit multiple data.

The device is selected when the chip enable (CE) line is low.

Additionally the (SO) is placed in a tri-state mode when the device is deselected. The

negative edge of the (CE) transfers the voltage level of the drivers to the shift register and

the positive edge of the (CE) latches the new data from the shift register to the drivers.

When CE is Low, data bit contained into the shift register is transferred to SO output at every

SCLK positive transition while data bit present at SI input is latched into the shift register on

every SCLK negative transition.

4.1

Internal blocks description

The internal architecture of the device is based on the three internal major blocks:

1.

the octal shift register for talking to the SPI bus,

2.

the octal latch for holding control bits written into the device

3.

the octal load driver array.

4.2

Shift register

The shift register has both serial and parallel inputs and serial and parallel outputs. The

serial input accepts data from the SPI bus and the serial output simultaneously sends data

into the SPI bus. The parallel outputs are latched into the parallel latch inside the L9822E at

the end of a data transfer. The parallel inputs jam diagnostic data into the shift register at the

beginning of a data transfer cycle.

4.3

Parallel latch

The parallel latch holds the input data from the shift register. This data then actuates the

output stages. Individual registers in the latch may be cleared by fault conditions in order to

protect the overloaded output stages. The entire latch may also be cleared by the RESET

signal.