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ATmega103(L) Errata

1436C–09/01

9.

Wrong Clearing of EXTRF in MCUSR

The EXTRF flag in MCUSR will be cleared when clearing the PORF-flag. The flag does not get cleared by writing a “0”

to it.

Problem Fix/Workaround

Finish the test of both flags before clearing any of them. Clear both flags simultaneously by writing “0” to both PORF

and EXTRF in MCUCR.

8.

Reset during EEPROM Write

If reset is activated during EEPROM write, the result is not what should be expected. The EEPROM write cycle com-

pletes as normal, but the address registers are reset to 0. The result is that both the address written and address 0 in

the EEPROM can be corrupted.

Problem Fix/Workaround

Avoid using address 0 for storage, unless you can guarantee that you will not get a reset during EEPROM write.

7.

SPI Interrupt Flag Can be Undefined after Reset

In certain cases when there are transitions on the SCK pin during reset, or the SCK pin is left unconnected, the start-up

value of the SPI interrupt flag is unknown. If the flag is not reset before enabling the SPI interrupt, a pending SPI inter-

rupt may be executed.

Problem Fix/Workaround

Clear the SPI interrupt flag before enabling the interrupt.

6.

Skip Instruction with Interrupts

A skip instruction (SBRS, SBRC, SBIS, SBIC, CPSE) that skips a two-word instruction needs three clock cycles. If an

interrupt occurs during the first or second clock cycle of this skip instruction, the return address will not be stored cor-

rectly on the stack. In this situation, the address of the second word in the two-word instruction is stored. This means

that on return from interrupt, the second word of the two-word command will be decoded and executed as an instruc-

tion. The ATmega103 has four two-word instructions: LDS, STS, JMP, and CALL.

Notes:

1.

This can only occur if all of the following conditions are true:

- A skip instruction is followed by a two-word instruction.

- The skip instruction is actually skipping the two-word instruction.

- Interrupts are enabled, and at least one interrupt source can generate an interrupt.

- An interrupt arrives in the first or second cycle of the skip instruction.

2.

This will only cause problems if the address of the following LDS or STS command points to an address beyond

400 Hex.

Problem Fix/Workaround

For assembly program, avoid skipping a two-word instruction if interrupts are enabled.

The following C-compilers handles this sequence correctly:

- IAR Compiler, version 1.40b or higher

- Image Craft compiler, all versions

- Codevision Compiler, version 1.0.0.5 or higher

5.

Signature Bytes

The signature bytes of the first few lots of the ATmega103 have been shipped with wrong signature bytes. Also in the

datasheet, the wrong signature bytes have been given. The correct signature bytes are: $1E $97 $01.

Problem Fix/Workaround

Programmers must allow both $1E $97 $01 and $1E $01 $01 as valid signature bytes.