IDT71342LA55J datasheet(9/13 Pages) IDT

9 / 13 page

6.05

IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)

NOTES:

CE = VIH for the duration of the above timing (both write and read cycle).

2. "DATAOUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.

NOTES:

1. D0R = D0L = VIL,

CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.

2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

3. This parameter is measured from the point where R/

W "A" or SEM "A" goes High until R/W "B" or SEM "B" goes High.

4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.

A0"A" - A2"A"

tSPS

W "A"

SEM "A"

"A"

SIDE

(2)

A0"B" - A2"B"

W "B"

SEM "B"

"B"

SIDE

MATCH

2721 drw 13

(2)

TIMING WAVEFORM OF SEMAPHORE CONTENTION(1, 3, 4)

A0 - A2

VALID ADDRESS

DATAIN VALID

DATAOUT

VALID

SEM

DATA0

tAW

tEW

tWR

tDW

tDH

tWP

tAS

tSWRD

tSOP

tAOE

tACE

tSAA

tOH

Test Cycle

(Read Cycle)

Write Cycle

2721 drw 12

(2)

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