80960CF-40 datasheet(16/77 Pages) INTEL

16 / 77 page

PRELIMINARY

80960CF-40, -33, -25, -16

CLKIN

A(E)

H(Z)

R(Z)

CLOCK INPUT is an input for the external clock needed to run the processor. The

external clock is internally divided as prescribed by the CLKMODE pin to produce

PCLK2:1.

CLKMODE

A(L)

H(Z)

R(Z)

CLOCK MODE selects the division factor applied to the external clock input (CLKIN).

When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and the

processor’s internal clock. When CLKMODE is low, CLKIN is divided by two to create

PCLK2:1 and the processor’s internal clock. CLKMODE should be tied high or low in

a system as the clock mode is not latched by the processor. If left unconnected, the

processor internally pulls the CLKMODE pin low, enabling the 2-x clock mode.

PCLK2:1

H(Q)

R(Q)

PROCESSOR OUTPUT CLOCKS provide a timing reference for all inputs and

outputs. All input and output timings are specified in relation to PCLK2 and PCLK1.

PCLK2 and PCLK1 are identical signals. Two output pins are provided to allow flexi-

bility in the system’s allocation of capacitive loading on the clock. PCLK2:1 may also

be connected at the processor to form a single clock signal.

VSS

–

GROUND connections must be connected externally to a VSS board plane.

VCC

–

POWER connections must be connected externally to a VCC board plane.

VCCPLL

–

VCCPLL is a separate VCC supply pin for the phase lock loop used in 1-x clock mode.

Connecting a simple lowpass filter to VCCPLL may help reduce clock jitter (TCP) in

noisy environments. Otherwise, VCCPLL should be connected to VCC.

–

NO CONNECT pins must not be connected in a system.

Table 3. 80960CF Pin Description — Processor Control Signals (Sheet 2 of 2)

Name

Type

Description

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