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80960JD データシート(PDF) 16 Page - Intel Corporation

部品番号 80960JD
部品情報  EMBEDDED 32-BIT MICROPROCESSOR
PDF  61 Pages
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メーカー  INTEL [Intel Corporation]
ホームページ  http://www.intel.com
Logo INTEL - Intel Corporation

80960JD データシート(HTML) 16 Page - Intel Corporation

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80960JD
Table 5. Pin Description — Interrupt Unit Signals
NAME
TYPE
DESCRIPTION
XINT7:0
I
A(E/L)
EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT7:0
pins can be configured in three modes:
Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs
can be programmed to be level (low) or edge (falling) sensitive.
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins
are level sensitive in this mode.
Mixed Mode:
The XINT7:5 pins act as dedicated sources and the XINT4:0 pins
act as the five most significant bits of a vectored source. The least
significant bits of the vectored source are set to 010
2 internally.
Unused external interrupt pins should be connected to V
CC.
NMI
I
A(E)
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt source and is falling edge-triggered. If NMI is
unused, it should be connected to VCC.



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