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CDP1823CD3 データシート(PDF) 4 Page - Intersil Corporation

部品番号 CDP1823CD3
部品情報  High-Reliability CMOS 128-Word x 8-Bit Static RAM
PDF  6 Pages
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メーカー  INTERSIL [Intersil Corporation]
ホームページ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CDP1823CD3 データシート(HTML) 4 Page - Intersil Corporation

  CDP1823CD3 Datasheet HTML 1Page - Intersil Corporation CDP1823CD3 Datasheet HTML 2Page - Intersil Corporation CDP1823CD3 Datasheet HTML 3Page - Intersil Corporation CDP1823CD3 Datasheet HTML 4Page - Intersil Corporation CDP1823CD3 Datasheet HTML 5Page - Intersil Corporation CDP1823CD3 Datasheet HTML 6Page - Intersil Corporation  
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6-34
Access Time from MRD (Note 1)
tAM
5
-
310
-
435
ns
Data Hold Time After Read
tDH
5
50
-
70
-
ns
NOTE:
1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.
Read Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF (Continued)
PARAMETER
SYMBOL
VDD
(V)
LIMITS
UNITS
+25oC, -55oC
+125oC
MIN
MAX
MIN
MAX
ADDRESS
tRC
tAA
tAM
(NOTE 1)
MRD
tAC
CS2, CS3, CS5
CS1, CS4
tDH
HIGH IMPEDANCE
VALID DATA
90%
10%
NOTES:
1. Minimum timing for valid data output. Longer times will initiate an earlier but invalid output.
2. MWR is high during read operation. Timing measurement reference is 0.5VDD.
FIGURE 1. READ CYCLE TIMING DIAGRAM
(NOTE 1)
Write Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF
PARAMETER
SYMBOL
VDD
(V)
LIMITS
UNITS
+25oC, -55oC
+125oC
(NOTE 2)
MIN
MAX
(NOTE 2)
MIN
MAX
Write Cycle
tWC
5
280
-
400
-
ns
Address Setup Time (Note 1)
tAS
5
70
-
100
-
ns
Address Hold Time
tAH
5
70
-
100
-
ns
Write Pulse Width (Note 1)
tWW
5
140
-
200
-
ns
Data to MWR Setup Time (Note 1)
tDS
5
70
-
100
-
ns
CDP1823C/3



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