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CDP1854AC/3 データシート(PDF) 14 Page - Intersil Corporation

部品番号 CDP1854AC/3
部品情報  Programmable Universal Asynchronous Receiver/Transmitter (UART)
PDF  21 Pages
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メーカー  INTERSIL [Intersil Corporation]
ホームページ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CDP1854AC/3 データシート(HTML) 14 Page - Intersil Corporation

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5-55
Mode Input Low (Mode = 0)
NOTE:
1. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0.
FIGURE 6. MODE 1 CPU INTERFACE (READ) TIMING DIAGRAM
tRST
tTRS
tTT
tRSDV
TPB
R BUS 0-
R BUS 7
CS2
RD/WR, CS1, CS3
(NOTE 1)
RSEL
tRDV
tRDDA
tRDH
FIGURE 7. MODE 0 BLOCK DIAGRAM (INDUSTRY STANDARD COMPATIBLE)
CONTROL
REGISTER
26
TRANSMITTER
HOLDING REGISTER
TRANSMITTER BUS
TRANSMITTER
SHIFT
REGISTER
PARITY
GEN
RECEIVER BUS
TRANSMITTER
TIMING AND
CONTROL
40
T CLOCK
TRANSMITTER SECTION
RECEIVER
TIMING AND
CONTROL
17
RECEIVER SECTION
RECEIVER
HOLDING
REGISTER
20
SDI
25
SDO
27 28 29 30 31 32 33
35 36 39 38 37
23
THRL
CRL
SFD
STATUS
REGISTER
22 24 13 14 15
DAR
R CLOCK
RECEIVER
SHIFT
REGISTER
19
5
THREE-STATE
DRIVERS
6
7
8
9 10 11 12
RRD
4
18
16
34
1 = VDD
2, 3 = VSS
21 = MR
CDP1854A, CDP1854AC



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