DG201 datasheet(4/7 Pages) INTERSIL

4 / 7 page

Typical Applications

Using the VREF Terminal

The DG201 has an internal voltage divider setting the TTL

threshold on the input control lines for V+ equal to +15V. The

schematic shown in Figure 4 with nominal resistor values,

gives approximately 2.4V on the VREF pin. As the TTL input

signal goes from +0.8V to +2.4V, Q1 and Q2 switch states to

turn the switch ON and OFF. If the power supply voltage is

less than +15V, then a resistor (REXT) must be added

between V+ and the VREF pin, to restore +2.4V at VREF.

The table shows the value of this resistor for various supply

voltages, to maintain TTL compatibility. If CMOS logic levels

with a +5V supply are being used, the threshold shifts are

less critical, but a separate column of suitable values is given

in the table. For logic swings of -5V to + 5V, no resistor is

needed.

In general, the “low” logic level should be <0.8V to prevent

Q1 and Q2 from both being ON together (this will cause

incorrect switch function).

Test Circuits

FIGURE 1. tON AND tOFF TEST CIRCUIT

FIGURE 2. CHARGE INJECTION TEST CIRCUIT

FIGURE 3. OFF ISOLATION TEST CIRCUIT

LOGIC

INPUT

ANALOG

INPUT 10V

10pF

VOUT

Ω

LOGIC

INPUT

ANALOG

INPUT 10V

10nF

VOUT

100

Ω

2VP-P AT 1MHz

LOGIC

INPUT

Ω

ANALOG INPUT

TABLE 1.

V+ SUPPLY (V)

REXT FOR TTL

LEVELS (k

Ω)

REXT FOR CMOS

LEVELS (k

Ω)

+15

+12

420

+10

190

136

V+

118k

Ω

VREF

23k

Ω

REXT

GATE

PROTECTION

RESISTOR

INPUT

FIGURE 4.

DG201

DG201 データシート(PDF) 4 Page - Intersil Corporation

DG201 データシート(HTML) 4 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6 7

データシートダウンロード

リンク URL

DG201 データシート(PDF) 4 Page - Intersil Corporation

DG201 データシート(HTML) 4 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6 7

データシート ダウンロード

リンク URL

データシートダウンロード