ADG749

Data Sheet

Rev. C | Page 12 of 12

OUTLINE DIMENSIONS

1.30 BSC

COMPLIANT TO JEDEC STANDARDS MO-203-AB

1.00

0.90

0.70

0.46

0.36

0.26

2.20

2.00

1.80

2.40

2.10

1.80

1.35

1.25

1.15

0.10 MAX

1.10

0.80

0.40

0.10

0.22

0.08

3

1

2

4

6

5

0.65 BSC

COPLANARITY

0.10

SEATING

PLANE

0.30

0.15

Figure 23. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-6)

Dimensions shown in millimeters

ORDERING GUIDE

Model1

Temperature range

Package Description

Package Option

Branding2

ADG749BKSZ-R2

−40°C to +125°C

6-Lead Thin Shrink Small Outline Transistor Package [SC70]

KS-6

S1M

ADG749BKSZ-REEL

−40°C to +125°C

6-Lead Thin Shrink Small Outline Transistor Package [SC70]

KS-6

S1M

ADG749BKSZ-REEL7

−40°C to +125°C

6-Lead Thin Shrink Small Outline Transistor Package [SC70]

KS-6

S1M

1

Z= RoHS Compliant Part.

2

Branding on this package is limited to three characters due to space constraints.

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registered trademarks are the property of their respective owners.

D02075-0-12/11(C)