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SPC564Axx/SPC56ELxx exception cases

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Figure 4. Flash 2b ECC error

3.1.2

Machine check exception status

3.1.3

Flash 2b ECC error detection by ECSM

Flash controller provides detection ability of ECC errors detection.

Table 5. Flash 2b ECC - machine check exception status in core registers

Register

Description

MCSRR0

Address of the instruction that caused the exception. In case of ECC error in the

data flash area, register modification is needed.

MCSR

Type of operation is highlighted here, instruction fetch, data load or data write.

MCAR

Target address that was accessed, but finished with 2b ECC error. This address

can be used for further analysis.

Table 6. Flash 2b ECC – ECSM registers related to ECC error detection

Register

Description

ECSM_ESR

The ECSM_ESR signals the last, properly enabled (in ECSM_ECR) memory

event to be detected. RAM and Flash single bit errors, as well as dual bit errors,

are signaled by separated status bits.

ECSM_ESR.R1BC A reportable single-bit platform RAM correction has been detected.

ECSM_ESR.RNCE A reportable non-correctable platform RAM error (2b ECC) has been detected.