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AN2352 データシート(PDF) 17 Page - STMicroelectronics

部品番号 AN2352
部品情報  PLL jitter effects on C-CAN modules of the ST10F27x
PDF  20 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
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AN2352 データシート(HTML) 17 Page - STMicroelectronics

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AN2352
ST10F27x PLL jitter effect in CAN protocol
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ST10F27x PLL jitter effect in CAN protocol
The CAN protocol provides a mechanism to resynchronize from recessive to dominant after
every edge, as explained in
Section 1.3: Phase buffer segments and synchronization. The
two phase buffers and the synchronization jump make it possible to compensate the
oscillator or PLL tolerance.
Considering only the PLL effects, the C-CAN module present in the ST10F27x can always
compensate its PLL jitter. In the worst case, in fact, the long term jitter is +/- 4.5ns (
Figure 5
on page 16). From the jitter point of view, one of the worst CAN bit time configurations is
when tBT = 25tq, SJW = 1, tSJW = 1tq = 40ns. Considering that the summarized difference
between the receiver and the transmitter is 9ns, Synchronization Jump Width is sufficient to
compensate that difference. In other words, the numerator of the second term of the formula
(
Section 1.4: System clock tolerance range):
is always positive, leading in any case to a system clock tolerance range. In the same way if
tBT = 1µ, tBT = 18tq, tPB2 =1tq, the numerator of the second term of the formula:
is always positive, leading again to a system clock tolerance range.
3.1
System clock tolerance range reduction in presence of PLL
jitter
Even if the C-CAN module always compensates its PLL jitter, the system clock tolerance
range is nevertheless reduced, increasing the probability of errors. This section evaluates
that reduction and also provides two examples of configuration already dealt with in
Section 1.6: Calculation of the bit timing parameters.
3.1.1
Range reduction percentage
The above equations have been calculated starting from the relations of the system clock
tolerance range. Those quantities cannot be higher than 22.5% (worst case:
δ
PLL = 4.5ns,
tSJW = min(tPB1,tPB2) = 40ns).
df
tSJW
()
2
δPLL
⋅
()
–
210
tBT
⋅⋅
--------------------------------------------------------
<
df
min tPB1 tPB2
,
()
2
δPLL
⋅
()
–
213
tBT tPB2
–
⋅
()
⋅
()
------------------------------------------------------------------------------------
<
df
dfPLL
–
df
----------------------------
2
δPLL
⋅
tSJW
-------------------------
=
df
dfPLL
–
df
----------------------------
2
δPLL
⋅
min tPB1 tPB2
,
()
------------------------------------------------
=



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