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AN3959 データシート(PDF) 31 Page - STMicroelectronics |
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AN3959 データシート(HTML) 31 Page - STMicroelectronics |
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31 / 65 page ![]() AN3959 Design guidelines for schematic and PCB layout Doc ID 022081 Rev 3 31/65 6.1.7 Recommended power-up and power-down sequence There is no constraint regarding power supply voltages while it is required to release the reset line (RST) only after the master clock (MCLK) is stable, after the power-down (PWDN) is already set high and before any I2C commands. Figure 32. Recommended power-up and power-down sequence 6.2 Layout The following figures illustrate layout recommendations. Figure 33. Snubber network soldered as close as possible to the respective IC pin |
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