DocID025366 Rev 2

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AN4374

Output error detection

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Figure 19. LED1642GW and ALED1642GW error detection: combined detection start

Figure 20. LED1642GW and ALED1642GW error detection: detection end

Clk

LE

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

first bit

last bit

Combined detection start: 11 CLK rising edges when the LE is “1”

Data signal doesn't care; LE is high for 11 clock rising edges

AM16868v1

Clk

LE

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

first bit

last bit

Detection end: 12 CLK rising edges when the LE is “1” + 16 CLK rising edges for SDO data output

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Data signal doesn't care; LE is high for 12 clock rising edges on first 16-bit word

AM16869v1