UPD4724 datasheet(2/16 Pages) NEC

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µPD4724

BLOCK DIAGRAM/PIN CONFIGURATION (TOP VIEW)

VDD

VCC

–

GND

–

VSS

+10 V

+3.3 V

+5 V

DIN1

DIN2

DIN3

ROUT1

ROUT2

ROUT3

ROUT4

ROUT5

DOUT1

DOUT2

DOUT3

RIN1

RIN2

RIN3

RIN4

RIN5

Note

VCHA

STBY

–10 V

300

Ω

300

Ω

300

Ω

5.5 k

Ω

5.5 k

Ω

5.5 k

Ω

5.5 k

Ω

5.5 k

Ω

–

Note The pull-up resistors of the driver inputs are active resistors.

Remark 1.

VDD and VSS are pins that output the voltage boosted internally. Don't connect these pins to the

load.

Capacitors with a breakdown voltage of 20 V or higher are recommended for C1 to C5. And it is

recommended to insert the capacitor that is 0.1

µF to 1 µF between VCC and GND.

The capacitor C5 does not have to be connected when the IC is used in 5 V mode (VCHA = L).

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