6 Reference Design

AN1775

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6.9

Flash

One Flash 2M word is connect to External Interface Memoy EMI and mapped from 0x6000

0000 to 0x603F FFFF (boot bank).

For more details, refer toFlash memory M28W320ECB datasheet.

6.10

LCD interface

LCd 2 * 16 is connected to external interface memory EMI.

Address 2 A2 is used as the LCD register address signal.

Region space available from 0x6400 0000 to 0x65FF FFFF

6.11

Conclusions and recommendations

●

System clock jitter values decrease when the system clock is delivered by STR71x internal

PLL1 (comparing to the jitter values on the external oscillator inputs), because the noise

injected in the CLK pin input was filtered by the internal PLL.

●

It is possible to use one single external 4MHz oscillator to generate both core, peripheral’s

clocks and 48MHz USB clock to minimize and save board cost and space.

●

With this single external oscillator generating both the system clock using PLL1 and the

48Mhz USB clock using PLL2, the STR710/STR711 has all the characteristics to pass the

requirements for USB revision 2.0 full speed device test and get the USB certification.

Particular care must be taken to decrease external oscillator noise while routing its clock on

board.