AN3261 datasheet(9/17 Pages) STMICROELECTRONICS

9 / 17 page

AN3261

Typical application diagrams

Doc ID 17837 Rev 1

9/17

Figure 6.

Timing diagram - three push-button Smart Reset™

2.4

Input pull-up considerations (CMOS/fixed levels)

Inputs without internal pull-up resistors can be pulled to a different voltage level than the

supply voltage of the STM65xx devices, however:

●

the input pull-up voltage level should not exceed 5.5 V

●

the input logic levels specifications must be respected:

–VIHmin = 0.7VCC, VILmax = 0.3VCC in case of standard CMOS input cells (it is

recommended to always keep VIL on the ground level and VIH on the VCC level)

–VIHmin = 0.85 V, VILmax = 0.3 V in case of the fixed-logic levels devices

(STM6520, STM6522).

2.5

Output pull-up considerations

Open-drain RST outputs without internal pull-up resistors can also be pulled up to any

voltage independent of VCC (higher or lower than VCC) (but absolute maximum ratings must

be respected). The STM65xx devices can thus serve also as a simple level shifter.

Push-

button 1

tSRC

tREC

Push-

button 2

Push-

button 3

RST

AN3261 データシート(PDF) 9 Page - STMicroelectronics