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UPD70741 データシート(PDF) 39 Page - NEC |
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UPD70741 データシート(HTML) 39 Page - NEC |
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39 / 112 page  µPD70741 39 CSIM D Q SI SO SCLK 1 2 /2 φ φ INTCSI CTXE CRXE SOT MOD CLS Internal bus SO latch Shift register (SIO) Serial clock control circuit Baud rate generator Serial clock counter Interrupt control circuit 8.3 Synchronous Serial Interface (CSI) 8.3.1 Features High-speed transfer 6.25 Mbps maximum (when φ/2 is used with φ = 25 MHz) Half-duplex communication Character length: 8 bits Switchable between the MSB and LSB to lead data transfer Allows selection between external serial clock input and internal serial clock output Three-wire method SO : Serial data output SI : Serial data input SCLK : Serial clock I/O pin One interrupt source • Interrupt request signal (INTCSI) Figure 8-2. Block Diagram of Clock Synchronous Serial Interface |
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