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RM0319 データシート(PDF) 256 Page - STMicroelectronics |
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RM0319 データシート(HTML) 256 Page - STMicroelectronics |
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256 / 368 page  Legacy IEEE 1284 parallel port (SPP) RM0319 256/368 Doc ID 022640 Rev 3 this data to the print head or any buffer memory. It is also possible for the processor to communicate to the external host if paper error or any other fault occurs. 20.4 Clocks The timing diagram for one cycle of data transfer is shown in Figure 90. The acknowledge signal ACKn goes low for 0.5µs (minimum). This timing is derived from an input clock (APB clock) of 83 MHz. The busy signal goes back low only when the processor stores this latched data and sends the appropriate control signal (see Control Register). Figure 90. Data transfer timing diagram 0.5us DATA STROBEn BUSY ACKn SELINn |
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