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AN4654

Peripheral migration

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3.2

System architecture

The STM32L0xx MCU family has been designed to target an entry-level market, with low-

power capabilities and easy handling. In order to fulfill this aim while keeping the advanced

M0+. Its small silicon area, coupled to a minimal code footprint, allows for low-cost

applications with 32-bit performance. Figure 1 shows the correspondence between the

series requires a recompilation of the code to avoid the use of unavailable features.

Figure 1. System architecture

Important modifications have been performed on the MCU organization too, starting by

switching from a Harvard to Von Neumann architecture, decreasing the system complexity,

or focusing on SW Debug in order to simplify this precise feature.

3.3

Memory mapping

The peripheral address mapping has been changed in the STM32L0 series. The main

change concerns the GPIOs which have been moved from the AHB bus to the IOPORT bus

to allow them to operate at the maximum speed.