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LT1162CSW データシート(PDF) 3 Page - Linear Technology |
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LT1162CSW データシート(HTML) 3 Page - Linear Technology |
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3 / 16 page  3 LT1160/LT1162 IUVOUT Undervoltage Output Leakage V + = 15V q 0.1 5 µA VUVOUT Undervoltage Output Saturation V + = 7.5V, IUVOUT = 2.5mA q 0.2 0.4 V VOH Top Gate ON Voltage VINTOP = 2V, VINBOTTOM = 0.8V q 11 11.3 12 V Bottom Gate ON Voltage VINTOP = 0.8V, VINBOTTOM = 2V q 11 11.3 12 V VOL Top Gate OFF Voltage VINTOP = 0.8V, VINBOTTOM = 2V q 0.4 0.7 V Bottom Gate OFF Voltage VINTOP = 2V, VINBOTTOM = 0.8V q 0.4 0.7 V tr Top Gate Rise Time VINTOP (+) Transition, VINBOTTOM = 0.8V, q 130 200 ns Measured at VTGATE DR (Note 4) Bottom Gate Rise Time VINBOTTOM (+) Transition, VINTOP = 0.8V, q 90 200 ns Measured at VBGATE DR (Note 4) tf Top Gate Fall Time VINTOP (–) Transition, VINBOTTOM = 0.8V, q 60 140 ns Measured at VTGATE DR (Note 4) Bottom Gate Fall Time VINBOTTOM (–) Transition, VINTOP = 0.8V, q 60 140 ns Measured at VBGATE DR (Note 4) tD1 Top Gate Turn-On Delay VINTOP (+) Transition, VINBOTTOM = 0.8V, q 250 500 ns Measured at VTGATE DR (Note 4) Bottom Gate Turn-On Delay VINBOTTOM (+) Transition, VINTOP = 0.8V, q 200 400 ns Measured at VBGATE DR (Note 4) tD2 Top Gate Turn-Off Delay VINTOP (–) Transition, VINBOTTOM = 0.8V, q 300 600 ns Measured at VTGATE DR (Note 4) Bottom Gate Turn-Off Delay VINBOTTOM (–) Transition, VINTOP = 0.8V, q 200 400 ns Measured at VBGATE DR (Note 4) tD3 Top Gate Lockout Delay VINBOTTOM (+) Transition, VINTOP = 2V, q 300 600 ns Measured at VTGATE DR (Note 4) Bottom Gate Lockout Delay VINTOP (+) Transition, VINBOTTOM = 2V, q 250 500 ns Measured at VBGATE DR (Note 4) tD4 Top Gate Release Delay VINBOTTOM (–) Transition, VINTOP = 2V, q 250 500 ns Measured at VTGATE DR (Note 4) Bottom Gate Release Delay VINTOP (–) Transition, VINBOTTOM = 2V, q 200 400 ns Measured at VBGATE DR (Note 4) Test Circuit, TA = 25°C, V + = VBOOST = 12V, VTSOURCE = 0V, CGATE = 3000pF. Gate Feedback pins connected to Gate Drive pins, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range. Note 1: For the LT1160, Pins 1, 10 should be connected together. For the LT1162, Pins 1, 7, 14, 20 should be connected together. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LT1160CN/LT1160IN: TJ = TA + (PD)(70°C/W) LT1160CS/LT1160IS: TJ = TA + (PD)(110°C/W) LT1162CN/LT1162IN: TJ = TA + (PD)(58°C/W) LT1162CS/LT1162IS: TJ = TA + (PD)(80°C/W) Note 3: IS is the sum of currents through SV +, PV+ and Boost pins. IBOOST is the current through the Boost pin. Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Typical Performance Characteristics and Applications Information sections. The LT1160 = 1/2 LT1162. Note 4: See Timing Diagram. Gate rise times are measured from 2V to 10V and fall times are measured from 10V to 2V. Delay times are measured from the input transition to when the gate voltage has risen to 2V or decreased to 10V. |
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