6

LTC1390

APPLICATIO S I FOR ATIO

transmission. Table 1 shows the various bit combinations

for channel selection.

Table 1. Logic Table for Channel Selection

CHANNEL STATUS

EN

B2

B1

B0

All Off

0

X

X

X

S0

1

0

0

0

S1

1

0

0

1

S2

1

0

1

0

S3

1

0

1

1

S4

1

1

0

0

S5

1

1

0

1

S6

1

1

1

0

S7

1

1

1

1

Digital Data Transfer Operation

The block diagram of Figure 3 shows the components

contained within the LTC1390 required for digital data

transfer. Digital data transfer operation can be performed

from Data 1 to Data 2 and vice versa as shown in Figure 4.

When CS is high, Buffer 1 is enabled and Buffer 2 is

disabled. The digital input data is fed into the 4-bit shift

register and then shifted to the MUX switches for channel

Figure 4. Digital Data Transfer Operation

selection or to Data 2 via Buffer 1 for data transfer. Data

appears at Data 2 after the fourth rising edge of the clock.

When CS is low, Buffer 2 is enabled and Buffer 1 is

disabled, thus digital input data is directly transferred from

Data 2 to Data 1 without any clock delay.

Multiplexer Expansion

Several LTC1390s can be daisy-chained to expand the

number of multiplexer inputs. No additional interface

ports are required for the expansion. Figure 5 shows two

LTC1390s connected at their analog outputs to form a 16-

to-1 multiplexer at the input to an LTC1286 A/D converter.

CLK

CS

DATA 1

Hi-Z

DATA OUT

DATA IN

DATA IN

1234

DATA OUT

LTC1390 • F04

DATA 2

4-BIT SHIFT

REGISTER

MUX

SWITCHES

LTC1390 • F03

BUFFER 1

BUFFER 2

DATA 2

CLK

CS

DATA 1

Figure 3. Simplified Block Diagram of the Digital Data

Transfer Operation

Figure 5. Daisy-Chaining Two LTC1390s for Expansion

To ensure that only one channel is switched on at any one

time, two sets of channel selection bits are needed for Data

as shown in Figure 6. The first data sequence is used to

switch off one MUX and the second data sequence is used

to select one channel from the other MUX, or vice versa.

In other words, if bit “ENA” is high and bit “ENB” is low,

one channel of MUX A is switched on and all channels of

MUX B are switched off. If bit “ENA” is low and bit “ENB”

is high, all channels of MUX A are switched off and one

channel of MUX B is switched on.

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

S0

S1

S2

S3

S4

S5

S6

S7

D

DATA 2

DATA 1

CS

CLK

GND

ANALOG

INPUTS

LTC1390

A

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

S0

S1

S2

S3

S4

S5

S6

S7

D

DATA 2

DATA 1

CS

CLK

GND

ANALOG

INPUTS

LTC1390

B

1

2

3

4

8

7

6

5

+IN

–IN

GND

CLK

CS

LTC1286

LTC1390 • F05

DATA

CLK

CS

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