6

LTC1536

the IC. Bypass to ground with

≥0.1µF ceramic capacitor.

used as a logic input with a 1V threshold. If unused it can

GND (Pin 4): Ground.

RST (Pin 5): Reset Logic Output. Active high CMOS logic

An external pull-down on the RST pin will drive this pin high.

RST (Pin 6): Reset Logic Output. Active low, open-drain

SOFT RESET

RESET

3

2

TO

POWER

DETECT

8

PBR

7

SRST

4

GND

REF

PBR

TIMER

200ms

RESET

GENERATOR

POWER

DETECT/

GATE DRIVE

6

RST

5

RST

6

µA

7

µA

6

µA

FAST

FAST

SLOW

FAST

SLOW

SLOW

1

TO POWER DETECT

1326 BD

Asserted when one or more of the supplies are below trip

thresholds and held for 200ms after all supplies become

valid. Also asserted after PBR is held low for more than two

seconds and for an additional 200ms after PBR is released.

SRST (Pin 7): “Soft” Reset. Active low, open-drain logic

after PBR is held low for less than two seconds and released.

PBR (Pin 8): Pushbutton Reset. Active low logic input with

when interfacing to 5V logic. When asserted for less than

two seconds, outputs a soft reset 100

µspulseontheSRST

pin. When PBR is asserted for greater than two seconds,

the RST output is forced low and remains low until 200ms

after PBR is released.