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LMS12JC40 データシート(PDF) 6 Page - LOGIC Devices Incorporated

部品番号 LMS12JC40
部品情報  12-bit Cascadable Multiplier-Summer
PDF  9 Pages
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メーカー  LODEV [LOGIC Devices Incorporated]
ホームページ  http://www.logicdevices.com
Logo LODEV - LOGIC Devices Incorporated

LMS12JC40 データシート(HTML) 6 Page - LOGIC Devices Incorporated

  LMS12JC40 Datasheet HTML 1Page - LOGIC Devices Incorporated LMS12JC40 Datasheet HTML 2Page - LOGIC Devices Incorporated LMS12JC40 Datasheet HTML 3Page - LOGIC Devices Incorporated LMS12JC40 Datasheet HTML 4Page - LOGIC Devices Incorporated LMS12JC40 Datasheet HTML 5Page - LOGIC Devices Incorporated LMS12JC40 Datasheet HTML 6Page - LOGIC Devices Incorporated LMS12JC40 Datasheet HTML 7Page - LOGIC Devices Incorporated LMS12JC40 Datasheet HTML 8Page - LOGIC Devices Incorporated LMS12JC40 Datasheet HTML 9Page - LOGIC Devices Incorporated  
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DEVICES INCORPORATED
LMS12
12-bit Cascadable Multiplier-Summer
Multiplier-Summers
08/16/2000–LDS.S12-J
6
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LMS12–
65*
50*
40*
Symbol
Parameter
Min
Max
Min
Max
Min
Max
tCP
Clock Period
40
35
30
tPW
Clock Pulse Width
15
15
12
tSAB
A, B, Data Setup Time
15
15
12
tSC
C Data Setup Time
15
15
12
tSEN
ENA, ENB, ENC Setup Time
15
15
12
tHAB
A, B, Data Hold Time
5
5
5
tHC
C Data Hold Time
5
5
5
tHEN
ENA, ENB, ENC Hold Time
5
5
5
tD
Clock to S–FT = 1
50
45
35
Clock to S–FT = 0
25
25
25
tENA
Three-State Output Enable Delay (Note 11)
25
25
25
tDIS
Three-State Output Disable Delay (Note 11)
22
22
22
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
SWITCHING WAVEFORMS
HIGH IMPEDANCE
INPUTS
A, B, C
tENA
tDIS
tPW
tSAB
tSC
tSEN
ENA
ENB, ENC
CLOCK
OE
tD
S OUTPUTS
tHEN
tPW
R OUTPUTS
tHAB
tHC
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*DISCONTINUED SPEED GRADE



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