9DBV0641 datasheet(9/17 Pages) ICST

9 / 17 page

REVISION B 09/11/14

6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS

9DBV0641 DATASHEET

Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics

Electrical Characteristics–Phase Jitter Parameters

TA = TAMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

-3dB point in High BW Mode

1.8

2.7

3.8

MHz

1,5

-3dB point in Low BW Mode

0.8

1.4

MHz

1,5

PLL Jitter Peaking

tJPEAK

Peak Pass band Gain

1.3

Duty Cycle

tDC

Measured differentially, PLL Mode

50.1

Duty Cycle Distortion

tDCD

Measured differentially, Bypass Mode @100MHz

-1

1,3

tpdBYP

Bypass Mode, VT = 50%

3000

3600

4500

tpdPLL

PLL Mode VT = 50%

-4

200

1,4

Skew, Output to Output

tsk3

VT = 50%

1,4

PLL mode

1,2

Additive Jitter in Bypass Mode

0.1

1,2

1 Guaranteed by design and characterization, not 100% tested in production.

2 Measured from differential waveform

3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

4 All outputs at default slew rate

5 The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.

Skew, Input to Output

Jitter, Cycle to cycle

tjcyc-cyc

PLL Bandwidth

TA = TAMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

INDUSTRY

LIMIT

UNITS

Notes

tjphPCIeG1

PCIe Gen 1

ps (p-p) 1,2,3,5

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.8

1.4

(rms)

1,2,3,5

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

2.3

2.5

3.1

(rms)

1,2,3,5

tjphPCIeG3

PCIe Gen 3 Common Clock Architecture

(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)

0.5

0.6

(rms)

1,2,3,5

tjphPCIeG3SRn

PCIe Gen 3 Separate Reference No Spread (SRnS)

(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)

0.5

0.6

0.7

(rms)

1,2,3,5

tjphSGMII

125MHz, 1.5MHz to 20MHz, -20dB/decade

rollover < 1.5MHz, -40db/decade rolloff > 10MHz

1.9

2N/A

(rms)

1,2,3,5

tjphPCIeG1

PCIe Gen 1

0.1

N/A

(p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.1

0.4

N/A

(rms)

1,2,5

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

0.01

0.4

N/A

(rms)

1,2,5

tjphPCIeG3

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.00

0.1

N/A

(rms)

1,2,4,5

tjphSGMIIM0

125MHz, 1.5MHz to 10MHz, -20dB/decade

rollover < 1.5MHz, -40db/decade rolloff > 10MHz

165

200

N/A

(rms)

1,6

tjphSGMIIM1

125MHz, 12kHz to 20MHz, -20dB/decade rollover

< 1.5MHz, -40db/decade rolloff > 10MHz

251

300

N/A

(rms)

1,6

1Guaranteed by design and characterization, not 100% tested in production.

4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]

5 Driven by 9FGV0831 or equivalent

6 Rohde&Schartz SMA100

2 See http://www.pcisig.com for complete specs

3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

Additive Phase Jitter

tjphPCIeG2

Phase Jitter, PLL Mode

tjphPCIeG2

9DBV0641 データシート(PDF) 9 Page - Integrated Circuit Systems

9DBV0641 データシート(HTML) 9 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

データシートダウンロード

リンク URL

9DBV0641 データシート(PDF) 9 Page - Integrated Circuit Systems

9DBV0641 データシート(HTML) 9 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

データシート ダウンロード

リンク URL

データシートダウンロード