9FGL02 datasheet(10/19 Pages) IDT

10 / 19 page

2-OUTPUT 3.3V PCIE GEN 1-2-3 CLOCK GENERATOR

REVISION A 07/17/15

9FGL02 DATASHEET

General SMBus Serial Interface Information

How to Write

• Controller (host) sends a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) sends the byte count = X

• IDT clock will acknowledge

• Controller (host) starts sending Byte N through Byte

N+X-1

• IDT clock will acknowledge each byte one at a time

• Controller (host) sends a Stop bit

Note: SMBus Read/Write Address is Latched on SADR

pin. Unless otherwise indicated, default values are for the

xx41 and xx51. P1 devices are fully factory

programmable.

How to Read

• Controller (host) will send a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) will send a separate start bit

• Controller (host) sends the read address

• IDT clock will acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends Byte N+X-1

• IDT clock sends Byte 0 through Byte X (if X(H) was

written to Byte 8)

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Write Operation

Controller (Host)

IDT (Slave/Receiver)

TstarT bit

Slave Address

WRite

ACK

Beginning Byte = N

ACK

Data Byte Count = X

ACK

Beginning Byte N

ACK

Byte N + X - 1

ACK

PstoP bit

Index Block Read Operation

Controller (Host)

IDT (Slave/Receiver)

TstarT bit

Slave Address

WRite

ACK

Beginning Byte = N

ACK

Repeat starT

Slave Address

ReaD

ACK

Data Byte Count=X

ACK

Beginning Byte N

ACK

Byte N + X - 1

Not acknowledge

PstoP bit

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