Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

4

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +5V ±10%, VSS = 0V to -5.5V, VREF = 4V, AGND = DGND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX,

unless otherwise noted.)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Positive Supply Voltage

SYMBOL

4.5

5.5

V

For specified performance

Negative Supply Voltage

-5.5

0

V

For specified performance

510

Positive Supply Current

512

mA

Negative Supply Current

mA

510

MAX5_ _C/E

MAX5_ _M

MAX5_ _C/E

512

MAX5_ _M

unloaded, all digital

Note 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.

Note 2: Input capacitance is code dependent. The highest input capacitance occurs at code = 00 hex.

code of all other DACs to 00 hex.

Note 5: Guaranteed by design.

Note 6: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.

TIMING CHARACTERISTICS

(VDD = +5V ±10%, VSS = 0V to -5V, VREF = 4V, AGND = DGND = 0V, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CLR Pulse Width Low

SYMBOL

50

25

ns

MAX5_ _M

MAX5_ _C/E

40

20

MAX5_ _M

50

25

ns

MAX5_ _C/E

40

20

SCLK Fall to

CS Rise Hold Time

0

ns

SCLK Fall to

CS Fall Hold Time

0

ns

(Note 7)

40

MAX5_ _C/E

10

100

MAX5_ _C/E

MAX5_ _C/E

40

40

MAX5_ _C/E

20

12.5

MAX5_ _C/E

DIN to SCLK Rise Hold Time

0

ns

SCLK Rise to

CS Rise Hold Time

(Note 9)

40

ns

LDAC Pulse Width Low

(Notes 7, 8)

0

ns

CS Rise to LDAC Fall Setup Time

40

MAX5_ _C/E

CS Fall to SCLK Setup Time

50

ns

MAX5_ _M

DIN to SCLK Rise Setup Time

50

ns

MAX5_ _M

SCLK Clock Frequency

20

10

MHz

MAX5_ _M

SCLK Pulse Width High

50

ns

MAX5_ _M

SCLK Pulse Width Low

MAX5_ _M

50

ns

SCLK to DOUT Valid

10

100

ns

MAX5_ _M

Note 7: Guaranteed by design.

Note 8: If

Note 9: Minimum delay from 12th clock cycle to

CS rise.

Outputs unloaded, all

POWER SUPPLIES

SERIAL INTERFACE TIMING