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ICS831724I データシート(PDF) 15 Page - Integrated Device Technology

部品番号 ICS831724I
部品情報  LVCMOS interface levels for all control inputs
PDF  24 Pages
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メーカー  IDT [Integrated Device Technology]
ホームページ  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS831724I データシート(HTML) 15 Page - Integrated Device Technology

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ICS831724AKI REVISION A MAY 16, 2013
15
©2013 Integrated Device Technology, Inc
ICS831724I Data Sheet
DIFFERENTIAL CLOCK DATA MULTIPLEXER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, HCSL, and other differential
signals. Both differential inputs must meet the VPP and VCMR input
requirements. Figures 2A to 2D show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 2A, the input termination
applies for IDT LVPECL drivers. If you are using an LVPECL driver
from another vendor, use their termination recommendation.
Figure 2A. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2C. CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 2B. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input
Driven by a 3.3V HCSL Driver
CLK
nCLK
Differential
Input
LVPECL
3.3V
Zo=50
Ω
Zo=50
Ω
3.3V
R1
50
Ω
R2
50
Ω
R2
50
Ω
3.3V
R1
100
Ω
LVDS
CLK
nCLK
3.3V
Receiver
Zo=50
Ω
Zo=50
Ω
3.3V
CLK
nCLK
3.3V
3.3V
LVPECL
Differential
Input
HCSL
*R3
*R4
CLK
nCLK
3.3V
3.3V
Differential
Input



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