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DB102 データシート(PDF) 4 Page - CML Microcircuits |
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DB102 データシート(HTML) 4 Page - CML Microcircuits |
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4 / 11 page ![]() Autocorrelating Signal Processor 4 MX102 © 1997 MX•COM,INC. www.mxcom.com Tele: 800 638 5577 910 744 5050 Fax: 910 744 5054 Doc.# 20480095.003 4800 Bethania Station road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. 2. Signal List Packages Signal Description DW/J Name Type 1 Signal In input The inverting input to the analog amplifier/comparator. Used with the Signal Bias pin; external coupling components are required. See Figure 2 3 Signal Bias output The output of the analogue amplifier/comparator. Do not load this pin with peripheral circuitry; there is no drive capacity for off-chip signaling. The feedback resistor should be not less than 200k Ω. See Figure 2. 4VDD power Positive supply rail. A single, stable power supply is required. Note that this device has two VDD pins; this input is positioned to prevent cross-talk, either or both may be connected to the host circuit's supply line. Do not attempt to draw current from either VDD pin. 5 BUFCLK output Buffered inverter oscillator digital output. May be used as test point to align clock frequency or to drive other circuitry. 6 XTAL output The output of the on-chip clock oscillator inverter. 8 Xtal/Clock input The input to the on-chip clock oscillator inverter; this may be a Xtal, resonator or clock pulse input. The selection of this frequency will affect the operational input signal bandwidth (and output frequency) of this device; refer to Table 4. Note that the choice of VDD will determine the maximum Xtal/clock frequency and hence the maximum useable signal input frequency. Operation of this microcircuit without an active Xtal or clock input may cause device damage. A clock pulse input is fed directly into this pin; Xtal/clock components are not required. See Table 2. 9VSS power Negative Supply 11 CLK ÷ 6 output A squarewave output clock signal at the rate of Clock/6; provided for peripheral and test purposes. 13 OUTPUT output (fOUT = 4 x fSIGNAL IN). The auto-correlated output signal at four times (x 4) the input signal (see Figure 3). There is a time delay between input and output signals (see Specifications). 16 VDD power Positive supply rail. A single, stable power supply is required. Note that this device has two VDD pins; either or both may be connected to the host circuit's supply line. Do not attempt to draw current from either VDD pin. The choice of VDD will determine the maximum Xtal/clock frequency and hence the maximum useable signal input frequency (see Figure 4). 2, 7, 10, 12, 14, 15 N/C No internal connection. Leave open circuit Table 1: Signal List |
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