PUSB3F96

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© NXP Semiconductors N.V. 2014. All rights reserved.

Product data sheet

Rev. 3 — 29 September 2014

8 of 15

NXP Semiconductors

PUSB3F96

ESD protection for ultra high-speed interfaces

The device uses an advanced clamping structure showing a negative dynamic resistance.

This snap-back behavior strongly reduces the clamping voltage to the system behind the

ESD protection during an ESD event. Do not connect unlimited DC current sources to the

data lines to avoid keeping the ESD protection device in snap-back state after exceeding

breakdown voltage (due to an ESD pulse for instance).

Fig 11. Dynamic resistance with positive clamping;

typical values

Fig 12. Dynamic resistance with negative clamping;

typical values

Fig 13. Dynamic resistance with positive clamping;

typical values

Fig 14. Dynamic resistance with negative clamping;

typical values

06

4

2

aaa-009371

2

4

6

(A)

0

-2.5

0

-0.5

-1.5

-1.0

-2.0

aaa-009372

-4

-2

0

(A)

-6

012

8

4

aaa-009373

14

I

(A)

0

2

4

6

8

10

12

-6

0

-2

-4

aaa-009374

0

I

(A)

-14

-12

-10

-8

-6

-4

-2