LP3961, LP3964

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SNVS056J – MAY 2000 – REVISED JUNE 2015

Feature Description (continued)

7.3.4 Dropout Voltage

The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within

2% of the output voltage. The LP3961 and LP3964 use an internal MOSFET with an Rds(on) of 240 m

Ω

(typically). For CMOS LDOs, the dropout voltage is the product of the load current and the Rds(on) of the internal

MOSFET.

7.3.5 Reverse Current Path

The internal MOSFET in LP3961 and LP3964 has an inherent parasitic diode. During normal operation, the input

voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is

pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets

forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to

200-mA continuous and 1-A peak.

7.4 Device Functional Modes

For the fixed output voltage products, the devices operate if the input voltage is equal to or exceeds

correctly and output voltage may not reach target value.

7.4.2 Operation With Shutdown (SD) Pin Control

A CMOS logic low level signal at the shutdown (SD) pin will turn off the regulator. The SD pin must be actively

terminated through a 10-k

Ω pullup resistor for a proper operation. This pin must be tied to the IN pin if not used .

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Product Folder Links: LP3961 LP3964