AR0130CSSC00SPBA0-DP datasheet(49/53 Pages) ONSEMI

49 / 53 page

AR0130 DS Rev. L Pub. 6/15 EN

©Semiconductor Components Industries, LLC, 2015.

AR0130: 1/3-Inch CMOS Digital Image Sensor

Power-On Reset and Standby Timing

Notes:

1. Xtal settling time is component-dependent, usually taking about 10 – 100 mS.

2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard

reset is held down by RC circuit, then the RC time must include the all power rail settle time and

Xtal settle time.

3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered

before or at least at the same time as the others. If the case happens that VDD_PLL is powered after

other supplies then sensor may have functionality issues and will experience high current draw on

this supply.

4. For the case where VDD_IO is 2.8V and VDD is 1.8V, it is recommended that the minimum time be

5s.

Table 19:

Power-Up Sequence

Definition

Symbol

Minimum

Typical

Maximum

Unit

VDD_PLL to VAA/VAA_PIX3

–

s

VAA/VAA_PIX to VDD

–

s

VDD to VDD_IO

–

s

VDD_IO to VDD_SLVS

–

s

Xtal settle time

–

301

–ms

Hard Reset

––

Internal Initialization

150000

–

EXTCLKs

PLL Lock Time

–

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