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SM5846AP データシート(PDF) 34 Page - Nippon Precision Circuits Inc

部品番号 SM5846AP
部品情報  Multi-function Digital Filter
PDF  36 Pages
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メーカー  NPC [Nippon Precision Circuits Inc]
ホームページ  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM5846AP データシート(HTML) 34 Page - Nippon Precision Circuits Inc

Back Button SM5846AP Datasheet HTML 28Page - Nippon Precision Circuits Inc SM5846AP Datasheet HTML 29Page - Nippon Precision Circuits Inc SM5846AP Datasheet HTML 30Page - Nippon Precision Circuits Inc SM5846AP Datasheet HTML 31Page - Nippon Precision Circuits Inc SM5846AP Datasheet HTML 32Page - Nippon Precision Circuits Inc SM5846AP Datasheet HTML 33Page - Nippon Precision Circuits Inc SM5846AP Datasheet HTML 34Page - Nippon Precision Circuits Inc SM5846AP Datasheet HTML 35Page - Nippon Precision Circuits Inc SM5846AP Datasheet HTML 36Page - Nippon Precision Circuits Inc  
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SM5846AP
NIPPON PRECISION CIRCUITS—34
Microprocessor Interface
Microprocessor interface pins
When MDS is LOW, the SM5846AP is controlled by
internal flags set by serial data transferred over the
microprocessor interface comprising MDLE, MDCK
and MDT.
Internal control flag serial data on MDT is input into
an internal shift register on the rising edge of
MDCK. After 8-bit data has been input, the data in
the shift register is stored in one of four internal flag
registers on the rising edge of MDLE latch enable.
The address of the flag register is derived by decod-
ing bits 1 to 3 of the 8-bit data.
Microprocessor interface
Microprocessor interface data input timing
MDCK and MDLE can also follow the dotted lines above
Pin name
Function
MDLE
Microprocessor data latch enable input
MDCK
Microprocessor data transfer clock input
MDT
Serial data input
Pin name
Function
Mode flag1
D-ATT Attenation
MDT
MDCK
D
Q
C
8bit SIPO Shift Register
8bit Register
8bit Register
8bit Register
Q
D
C
8bit Register
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Mode flag2
Mode flag3
Decoder
MDLE
bit1
bit2
bit3
bit4
bit5
bit6
bit7
bit8
MDLE
MDCK
MDT
MSB
LSB



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