3

SP5502

Table 1 Write data format (MSB transmitted first)

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Address

Programmable divider

Programmable divider

Charge pump and test bits

I/O port control bits

1

CP

X

0

T1

X

0

T0

P4

*

0

1

X

MA0

1

P1

MA1

1

P2

A

A

A

A

A

MSB

1

0

1

P7

LSB

0

OS

P0

*

Table 2 Read data format

Byte 1

Byte 2

Address

Status byte

1

FL

0

N

0

N

0

N

MA0

N

MA1

N

A

A

1

POR

1

N

Table 3 Address selection

MA0

0

1

0

1

MA1

0

0

1

1

Voltage input to P3

Open circuit

A

: Acknowledge bit

MA1, MA0

: Variable address bits (see Table 3)

CP

: Charge Pump current select

T1

: Test mode selection

T0

: Charge pump disable

OS

: Varactor drive Output disable Switch

P7, P4

Control output port states

POR

: Power On Reset indicator

FL

: Phase lock detect flag

X

: Don’t care

N

: Not valid

NOTES

† Programmed by connecting a 15k

Fig. 3 Data formats

The programmed frequency can be calculated by multiply-

ing the programmed division ratio by 8 times the comparison

When frequency data is entered, the phase comparator,

via the charge pump and varactor drive amplifier, adjusts the

local oscillator control voltage until the output of the program-

mable divider is frequency and phase locked to the comparison

frequency.

The reference frequency may be generated by an external

source capacitively coupled into pin 2 or provided by an on-

chip 4MHz crystal controlled oscillator.

Note that the comparison frequency is 7·8125kHz when a

4MHz reference is used.

Bit 2 of Byte 4 of the programming data (CP) controls the

current in the charge pump circuit, a logic 1 for

170µA and

a logic 0 for

50µA, allowing compensation for the variable

tuning slope of the tuner and also to enable fast channel

changes over the full band. Bit 4 of Byte 4 (T0) disables the

charge pump if set to a logic 1. Bit 8 of Byte 4 (OS) switches

the charge pump drive amplifier’s output off when it is set to

a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the

phase comparator inputs are available on P2 and P7, a logic

Byte 5 programs the output ports P0-P2, P4 and P7 on the

SP5502S (P1, P2 and P7 only on SP5502F), a logic 0 for a

high impedance output, logic 1 for low impedance (on).

READ MODE

When the device is in the read mode the status data read from

the device on the SDA line takes the form shown in Table 2. Bit

1 (POR) is the power supply to the device has dropped below a

nominal 3V and the programmed information lost (e.g., when the

device is initially turned on). The POR is set to 0 when the read

sequence is terminated by a stop command. The outputs are all

set to high impedance when the device is initially powered up. Bit

2 (FL) indicates whether the device is phase locked, a logic 1 is

present if the device is locked and a logic 0 if the device is

unlocked.