VP5313/VP5513

13

TIMING INFORMATION

Min.

Typ.

10

14.5

10

5

10

0

10

0

9

27.0

Max.

TBD

TBD

25

Units

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

PXCK

periods

ns

10% to 90% points

90% to 10% points

PXCK to COMPSYNC

PXCK to CLAMP

Conditions

Parameters

Master clock frequency (PXCK input)

PXCK pulse width, HIGH

PXCK pulse width, LOW

PXCK rise time

PXCK fall time

PD7-0 set up time

PD7-0 hold time

SCSYNC set up time

SCSYNC hold time

PALID set up time

PALID hold time

PALID duration

Output delay

Symbol

Figure 8 Closed Capation format

BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7

1

CLOCK RUN-IN

START BITS

13

DATA BYTE 1

DATA BYTE 2

0 1 0 0 0 0 1 1

FRAME CODE

B

CD

E

A

H

0

50

-40

IRE

HSYNC COLOUR BURST

S1

S2

S3

P

P

P = Parity Bit