CDCLVC1310_14 datasheet(8/30 Pages) TI1

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CDCLVC1310

SCAS917E – JULY 2011 – REVISED JANUARY 2014

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LVCMOS OUTPUT CHARACTERISTICS (continued)

over recommended ranges of supply voltage (VDDO

≤ VDD), load (50 Ω to VDDO/2), and ambient temperature (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDD = 3.3 V ±5%,

1.5

1.95

4.0

VDDO = 1.35 V to VDD

tDELAY

Output frequency

VDD = 2.5 V ±5%,

1.8

2.4

4.4

VDDO = 1.35 V to VDD

Single-ended input, VDD = 3.3 V,

VDDO = 3.3 V

Single-ended input, VDD = 2.5 V or

3.3 V, VDDO = 1.5 V, 1.8 V, or 2.5 V,

fIN/OUT = 125 MHz

tRJIT

System-level additive jitter(2)

fS, RMS

Differential input, VDD = 3.3 V,

VDDO = 3.3 V

Differential input, VDD = 2.5 V or

3.3 V, VDDO = 1.5 V, 1.8 V, or 2.5 V,

fIN/OUT = 125 MHz

10-kHz offset(3)

–145

100-kHz offset(3)

–156

1-MHz offset(3)

–163

10-MHz offset(3)

–164

20-MHz offset(3)

–164

Noise floor

dBc/Hz

10-kHz offset(4)

–145

100-kHz offset(4)

–155

1-MHz offset(4)

–160

10-MHz offset(4)

–161

20-MHz offset(4)

–162

odc

Output duty cycle

fIN/OUT = 125 MHz, idc = 50%

(5)

45%

55%

tEN

Output enable or disable time

Cycle

MUXISOLATION

MUX isolation(6)

125 MHz

(2)

Integration range: 12 kHz–20 MHz; input source see the System-Level Additive-Jitter Measurement section

(3)

Single-ended input, fIN/OUT = 125 MHz, VDD = VDDO = 3.3 V

(4)

Differential input, fIN/OUT = 125 MHz, VDD = VDDO = 3.3 V

(5)

Stable VIH, VIL, and VCM

(6)

See Figure 18.

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