TSA7887 datasheet(13/21 Pages) SILABS

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TSA7887

TSA7887 Rev. 1.0

Page 13

driving the CS pin from one of the host processor’s

port lines and ensuring that the serial data read

(from the microcontroller’s serial port) is not initiated

for at least 5

μs.

In DSP applications, where the CS signal is derived

typically from the DSP’s serial frame synchronization

port, it is usually not possible to separate a high-to-

low CS transition and a second low-to-high SCLK

transition by up to 5

μs without affecting the DSP

system serial clock speed. Therefore, system timing

design

should

incorporate

WRITE

the

TSA7887’s control register to terminate PM Mode 1

operation and program the ADC into PM Mode 2;

that is, by writing [PM1,PM0] = [0,1] into the

TSA7887’s

control

get

valid

conversion result, a second conversion must be

initiated when the ADC is powered up. A WRITE

operation

that

takes

place

with

this

second

conversion can program the ADC back into PM

Mode 1 where the power-down operation is enabled

when the CS pin is toggled high

Power Management Mode 2 Operation:

[PM1,PM0] = [0,1]

Regardless of the status of the CS signal, the

TSA7887 remains fully powered up in this mode of

operation. PM Mode 2 should be used for fastest

throughput rate performance because the system

timing design does not need to incorporate the

TSA7887’s 5-

μs power-up delay time. Figure 10

shows the general operating diagram for the

TSA7887 in PM Mode 2.

Serial data programmed into the TSA7887 at the

DIN input during the first eight clock cycles of data

transfer are loaded to the control register. For the

TSA7887 to remain in PM Mode 2, system timing

design must always write [PM1, PM0] = [0,1] into the

control register on every serial input data transfer.

A high-to-low CS transition initiates the conversion

sequence and the analog input signal is sampled on

the second low-to-high SCLK transition. Sixteen

serial clock cycles are required to complete the

conversion and to transfer the conversion result to

the host processor. Another conversion can be

initiated immediately by toggling the CS pin low

again once data transfer is complete (that is, once

the CS signal is toggled high).

Power Management Mode 3 Operation: [PM1,

PM0] = [1,0]

In this mode, the TSA7887 is automatically powered

down at the end of every conversion. It is similar to

PM Mode 1 except that the status of the CS signal in

PM Mode 3 does not have any effect on the power-

down status of the TSA7887.

Figure 11 shows the general operating diagram of

the TSA7887 in PM Mode 3. On the first high-to-low

SCLK

transition

after

toggled

low,

all

TSA7887’s internal circuitry starts to power up.

Similarly to PM Mode 1, it can take as long as 5

μs

for the TSA7887’s internal circuitry to power up

completely. As a result, any conversion start

sequence should not be initiated during this initial

μs power-up delay. The analog input signal is

sampled on the second low-to-high SCLK transition

following the high-to-low CS transition. As shown in

Figure 18, system timing design should incorporate

a 5-

μs delay between the first high-to-low SCLK

transition

and

the

second

low-to-high

SCLK

transition after the high-to-low CS transition.

Figure 10: TSA7887’s Power Management Mode 2 Operation Diagram.

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