ACE24C128B/256B/512B

Two-wire Serial EEPROM

VER 1.4

7

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if

this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the

chip will return to a standby state.

DATA SECURITY:

The ACE24C128B/256B/512B has a hardware data protection scheme that allows the user to write

protect the entire memory when the WP pin is at VCC.

Write Operations

Byte Write:

A write operation requires an 8-bit data word address following the device address word and

acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then

clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0"

and the addressing device, such as a microcontroller, must terminate the write sequence with a stop

condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile

memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is

complete (see Figure 5 on page 7).

Page Write:

The 128K/256K EEPROM is capable of an 64-byte page writes, and 512K device is capable of an 128-

byte page writes.

A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition

after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data

word, the microcontroller can transmit up to 63 (128K/256K) or 127 (512K) more data words. The

EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the

page write aequence with a stop condition (see Figure 6 on page 7).

The data word address lower six (128K/256K) or seven (512K) bits are internally incremented following

the receipt of each data word. The higher data word address bits are not incremented, retaining the

memory page row location. When the word address, internally generated, reaches the page boundary,

the following byte is placed at the beginning of the same page. If more than 64 (128K/256K) or 128

(512K) data words are transmitted to the EEPROM, the data word

address will “roll over” and previous

data will be overwritten.

Acknowledge Polling:

Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge

polling can be initiated. This involves sending a start condition followed by the device address word. The

read/write bit is representative of the operation desired. Only if the internal write cycle has completed will

the EEPROM respond with a "0", allowing the read or write sequence to continue.

Read Operations

Read operations are initiated the same way as write operations with the exception that the read/write

select bit in the device address word is set to "1". There are three read operations: current address read,

random address read and sequential read.