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VS6663 データシート(PDF) 13 Page - STMicroelectronics |
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VS6663 データシート(HTML) 13 Page - STMicroelectronics |
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13 / 64 page  DocID022316 Rev 3 13/64 VS6663 Functional description 47 3 Functional description 3.1 External clock 3.1.1 Clock input type The external clock provided by the host to the VS6663 must be a DC coupled square wave and may also be RC-filtered. Figure 5. Clock input types 3.1.2 PLL and clock input The VS6663 has an embedded PLL block. This block generates all necessary internal clocks from an input range defined in Table 5. The value of the external clock frequency must be written to register 0x0136 (extclk_frequency_mhz). Pad Pad Extclk extclk Camera module Host processor Pad Pad Extclk extclk Camera module Host processor 1st option DC-coupled 2nd option DC-coupled and filtered pwrdn pwrdn pwrdn pwrdn Table 5. System input clock frequency range Minimum (MHz) Maximum (MHz) 6 27 |
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